Practical Makefiles, by example

Re:Practical Makefiles, by example by pdq on Wednesday April 01, 2015 @07:50PM (#9307788)

One other dependency often forgotten is on the Makefile itself. This way if the Makefile changes, everything gets rebuilt:

    DEPS = Makefile
    %.o: %.c $(DEPS)
        $(CC) $(CCFLAGS) -o $@ -c $<

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Re:Practical Makefiles, by example by exDM69 on Thursday April 02, 2015 @05:51AM (#9309584)

This may or may not be what you want, depending on the use case. If you change an important variable in the Makefile (e.g. CFLAGS), you might want to recompile everything. However, if you're just adding a new source file to the Makefile, you definitely do not want to rebuild everything.

I prefer to run `make clean` manually when necessary rather than adding a rule to rebuild everything "just in case". But I can imagine that this might be useful in some cases.

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Re:Practical Makefiles, by example by atrn on Thursday April 02, 2015 @06:58AM (#9309851)

I like to put CFLAGS/CXXFLAGS et al in separate files that just define the corresponding macro. These get included in the makefile which has dependencies added to rules that reference such a macro on the file that defines the macro. E.g. the .o rule for C++ has a dependency on the CXXFLAGS which defines CXXFLAGS. Change CXXFLAGS and things rebuild, mess with LDFLAGS and you re-link etc... Handy if you need it but you can end up with lots of little files.

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