Re:Tough Times on the Road to StarCraft
by Retric on Monday January 26, 2015 @10:27AM
(#8947453)
First latency is a round trip, so you need to think .25c not .5c. Second, reaching the DIMM is not enough you need to reach the worst case furthest bit on that DIMM.
At .25c 1ns = Less than 3 inches. A single DDR3 DIMM is ~6 inches wide and ~1 inch tall so that's not long enough to cover a single DIMM.
Look at that picture again, including clips and those dimm slots are 7 inches wide. The top edge of a DIMM is 1 inch over the MB. And the furthest dimm is ~2 inches further from the CPU. The trace from the CPU's on board memory controller to the MB is ~1 inch. And the CPU is ~ 2 inches from the DIMMS.
At .25c 1ns = Less than 3 inches. A single DDR3 DIMM is ~6 inches wide and ~1 inch tall so that's not long enough to cover a single DIMM.
Look at that picture again, including clips and those dimm slots are 7 inches wide. The top edge of a DIMM is 1 inch over the MB. And the furthest dimm is ~2 inches further from the CPU. The trace from the CPU's on board memory controller to the MB is ~1 inch. And the CPU is ~ 2 inches from the DIMMS.
EDIT: http://en.wikipedia.org/wiki/DDR3_SDRAM#mediaviewer/File:4GB... The DIMMs are not strait paths so that can easily be another inch.
Looks close to 1 foot to me which at .25c that's ~4ns. Or 40% of the minimum latency.
As to layout, that stuff is much harder than you might think as the wires can't go over each other.