For completeness, generally memory access that misses the last level cache incurs 60-110 ns latency on recent DDR3 based x86 hardware, see eg. http://www.sisoftware.co.uk/?d=qa&f=ben_mem_latency&l=en&a=

I don't know what exactly the 32ns measurement is from, sounds similar to the "in-page" figures on the above page.