Hi. I think this UART can be made better. A typical hardware UART receiver is clocked at a multiple of the signalling rate (16x is common) and the pin is sampled according to the clock. During the middle of the bit period, marks on the bus affect a counter whose value is compared to a constant, the result of which indicates whether the majority of samples indicate a mark or a space. The result of this goes into the receive shift register. The samples from the beginning and the end of the bit period are discarded.

This mechanism allows for timing differences between either end, and some immunity to electrical noise.

Also, sampling and validating the stop bit(s) will reveal framing errors.