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Re:How Not to Measure Computer System Performance by rectang on Tuesday November 18, 2014 @06:11PM (#8627016)
I'd speculate that if you're unlucky about link order, two hot cache lines may get mapped to the same slot in an N-way associative cache -- whereas if you're lucky, they end up going to different slots and don't continuously evict each other.

With regards to alignment... do linkers typically pack objects so tightly that the start of each object isn't aligned on a cache line boundary? AFAIK they're typically 32, 64, or 128 bytes.

Re:How Not to Measure Computer System Performance by fleitz on Wednesday November 19, 2014 @04:46AM (#8629076)
Cacheline boundary?

Probably, because caches line sizes are an implementation detail, not part of the architectural specification.