Why Intel is adding instructions to speed up non-volatile memory

Re:Why Intel is adding instructions to speed up non-volatile... by JoeAltmaier on Thursday November 06, 2014 @07:57AM (#8566766)

How about: a cpu that has scores of hyperthreads? They don't block in the kernel; they stall on a semaphore register bitmask. That mask can include timer register matches another register; interrupt complete; event signaled.

Now I can do almost all of my I/o, timer and inter-process synchronization without ever entering a kernel or swapping out thread context. I've been waiting for this chip since the Z80.

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Re:Why Intel is adding instructions to speed up non-volatile... by rbanffy on Thursday November 06, 2014 @03:06PM (#8569428)

While not exactly a chip (it never reached board stage) I designed a processor in college where the register file was keyed to a task-id register. This way, context switches could take no longer than an unconditional jump.

I dropped this feature when I switched to a single-task stack-based machine (inspired by my adventures with GraFORTH - thank you, Paul Lutus). This ended up being my graduation project.

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