Re:How the Z80's registers are implemented
by TheLoneWolfling on Monday October 06, 2014 @09:08AM
(#8415633)
Meh, at least it's sublinear latency with the number of bits. (I'm assuming, based on the description. Unless there's something I'm missing, you've got log2(d) stages of O(1) latency.)
The nasty operations are the ones that are linear (or worse!).
The nasty operations are the ones that are linear (or worse!).