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A comment on RISC-V: An Open Standard for SoCs. Parent comment

Re:RISC-V: An Open Standard for SoCs by comex on Friday August 08, 2014 @01:39AM (#8151619)
> Variable-length instructions are especially beneficial to code density, since often-used instructions can be encoded in fewer bytes,

Speaking of this, I find it interesting that ARM went back to a fixed 32-bit instruction width for ARMv8 (from 16/32 in Thumb-2). Any idea why they chose to do this?

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Re:RISC-V: An Open Standard for SoCs by rwmj on Friday August 08, 2014 @04:48AM (#8151983)
ARMv8 is targeted at very high end phones but mainly at servers (of course it will creep down into cheap feature phones eventually). My server has 16 GB of RAM which is small for an ARMv8 server. So memory pressure may be not such a problem.

However it's also worth saying that Cortex-A53 can run Thumb-2 instructions. Not sure about Cortex-A57.

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Re:RISC-V: An Open Standard for SoCs by wolfgke on Friday August 08, 2014 @09:52AM (#8152737)
According to http://en.wikipedia.org/wiki/ARM_Cortex-A57 the Cortex-A57 supports Thumb-2 instructions.
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