alu.vhd, lines 40 - 42

      -- arithmetic
       alu_results.add_result <= std_logic_vector( signed( nos ) + signed( tos ) );
       alu_results.sub_result <= std_logic_vector( signed( nos ) - signed( tos ) );

This logic can be done with one adder instead of two. In two's complement, invert the 2nd operand and assert the carry in.