Re:Evolutionary algorithms and analog electronic circuits
by TheLoneWolfling on Sunday July 27, 2014 @05:17PM
(#8093996)
Even with that setup you end up with overfitting after a point. I.e. instead of getting something that works on every FPGA of that type, you start getting things that work on the specific FPGAs you provide. The same thing happens in machine learning for things like recognizing photos: after a while your algorithm stops recognizing cars and starts just recognizing those specific photos of cars.
Ideally, you want to take a bunch of FPGAs, pull out a random subsample of them only for acceptance testing, and stop evolving the circuit when the performance on the acceptance testing subset starts getting worse.
Re:Evolutionary algorithms and analog electronic circuits
by Houshalter on Monday July 28, 2014 @02:44PM
(#8098594)
Even if it worked on the specific FPGAs you provide, it might not work reliably in different temperatures like the one in the article, or if the noise is slightly further away, etc.
There is no way to stop overfitting because it's difficult if not impossible to test it in every possible environment we want it to work under.
Re:Evolutionary algorithms and analog electronic circuits
by TheLoneWolfling on Monday July 28, 2014 @05:51PM
(#8099540)
There are ways to catch overfitting: https://en.wikipedia.org/wiki/Cross-validation_%28statistics...
Re:Evolutionary algorithms and analog electronic circuits
by Houshalter on Tuesday July 29, 2014 @07:59AM
(#8101753)
That's not really relevant to this. That is for selecting hyper-parameters for statistical models.
Re:Evolutionary algorithms and analog electronic circuits
by TheLoneWolfling on Tuesday July 29, 2014 @09:18AM
(#8102024)
I know the article doesn't mention it, but you can use the exact same techniques for preventing overfitting in machine learning.
Re:Evolutionary algorithms and analog electronic circuits
by Houshalter on Tuesday July 29, 2014 @09:57PM
(#8106007)
That's basically what I said, and this is optimization not machine learning. The problem is the genetic algorithm fits the the specifics of the FPGA and the environment it is optimized in, and doesn't work reliably in other environments or FPGAs.
This reminds me of Physically Unclonable Functions (PUFs) that tries to utilize differences in manufactured devices as a method of distinquishing unique devices. This is used for identification and authentication. There are for example PUFs that use differences in delays between logic blocks in FPGAs to generate unique responses to applied patterns/challenges.
See for example: http://en.wikipedia.org/wiki/Physical_unclonable_function