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Re:Emulating a 6502 with cycle-perfect timing by zellyn on Thursday May 29, 2014 @12:53PM (#7817175)
Nice set of articles: flagged as toread.

One quick note: with the visual6502 project (http://www.visual6502.org/), and the c-implementation (https://github.com/mist64/perfect6502), a fun way to test your emulator timing is to run it in parallel with the gate-level simulation, and compare them. For example, I do this with my golang 6502 emulator: https://github.com/zellyn/go6502/blob/master/tests/compare_t...

Re:Emulating a 6502 with cycle-perfect timing by paulannesley on Thursday May 29, 2014 @03:45PM (#7818195)
Nice project zellyn; I've got one with the same creative repo name: https://github.com/pda/go6502 ;) Mine currently makes no attempt at being cycle-accurate; it's basically the dev/test environment for a breadboard 6502 computer I'm working on.
Re:Emulating a 6502 with cycle-perfect timing by mattgodbolt on Thursday May 29, 2014 @06:49PM (#7819116)
Very nice. I used v6502 a lot as the article shows, but the real fun comes with the cycle-stretching, which AFAICT can't be simulated using v6502.
Re:Emulating a 6502 with cycle-perfect timing by zellyn on Wednesday June 11, 2014 @07:49PM (#7881096)
Hmmm. You should be able to pull the same lines up/down or pause the clock the way the real hardware does it.