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A comment on Adaptive Clocking in AMD’s Steamroller.

Re:Adaptive Clocking in AMD’s Steamroller by nkurz on Wednesday May 07, 2014 @02:50AM (#7708937)
6. Microarchitectural throttling to reduce current draw (e.g., Itanium processors issue fewer instructions during dI/dt events and vector units often take many cycles to ‘warm up’); this reduces IPC and can cause instruction scheduling challenges.

How literal is the 'warm up' for the vector units? I've occasionally seen this effect mentioned with regard to microbenchmarking, but never understood why this might be. Are vector units actually slowly activated over several cycles so as to reduce voltage droop?

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Re:Adaptive Clocking in AMD’s Steamroller by zurn on Wednesday May 07, 2014 @04:07AM (#7709106)
It's not literal even in Itanium's case, as it's about leveling the voltage droop and not temperature.

There can be many other kinds of run-ups to steady state happening in processors for microbenchmarks. Caches/TLBs, branch predictors, clock gating, macro scale voltage/frequency scaling, memory prefetching, power management in the system outside cpu, etc.

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