The prefetch is only serving as 6-byte padding here. The nopw instruction performs no memory access, it does not double as a prefetch.

There are remarkably few memory accesses actually being performed in that loop. The CPU is using store forwarding to cache the 'memory' accesses in the store buffer, which means most accesses are not even accessing L1 cache (if this were the case, we would not have such a low count of cycles per iteration).

The best result I've got is by inserting a 6-byte nopw right before the store:

    .L3:
	movq	counter(%rip), %rdx
	addq	%rax, %rdx
	addq	$1, %rax
	cmpq	$400000000, %rax
        nopw   0x1(%rax,%rax,1)
	movq	%rdx, counter(%rip)
	jne	.L3