Re:Intel i7 loop performance anomaly
by rayiner on Tuesday December 03, 2013 @06:47PM
(#6844054)
> Even with very pessimistic alignment, HSW should get well more than one instruction per clock from that loop.
Why? In Haswell, a store needs an AGU (ports 2, 3, or 7) and the store data unit (port 4). Even with perfect store-load forwarding, you can only write one value per cycle into the store buffer.
Why? In Haswell, a store needs an AGU (ports 2, 3, or 7) and the store data unit (port 4). Even with perfect store-load forwarding, you can only write one value per cycle into the store buffer.