No, they're really all registers; it's just some of them aren't usable with all instructions for some of the M profile cores. Specifically, ARMv6M cores (like the M0) only implement the Thumb1 instruction set (the 16 bit instructions) plus a few additions so they don't need any ARM mode instructions for exception handling etc. ARMv7M cores (like the M3) implement pretty much all of Thumb2, including the 32 bit versions of instructions which allow you to make much greater use of the high registers (at the cost of slightly larger code).

http://infocenter.arm.com/help/topic/com.arm.doc.qrc0006e/QR... is the Thumb 16-bit instruction set quick reference card, which seems to have a reasonable summary of which instructions have which register restrictions.