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A comment on Why Hardware Development Is Hard, Part 1: Verilog Is Weird. Parent comment

Re:Why Hardware Development Is Hard, Part 1: Verilog Is Weird by jck on Monday November 11, 2013 @06:10PM (#6714747)
You might be interested in cocotb, which is a "coroutine based cosimulation testbench environment for testing VHDL/Verilog RTL using Python".

cocotb is developed in part by Solarflare communications.

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