Why Hardware Development Is Hard, Part 1: Verilog Is Weird

Re:Why Hardware Development Is Hard, Part 1: Verilog Is Weird by dominicgs on Monday November 11, 2013 @09:33AM (#6711737)

I'm not sure what sort of project you're interested in, but we're currently building open source network taps using PHY ICs and an FPGA. As part of the project a USB 3.0 core is being developed to move captured data to a host system.