Exactly, the mentioned researchers haven't done anything with any schematics of the real Intel processor. It's "what we believe we could do if we'd have the control of the production of a processor with the RND like the one described by Intel to exist in their CPU's starting with their Ivy Bridge architecture."

Still, it's interesting to see how such things could be done.

The choice of BIST over scan/ATPG makes this attack theoretically possible on Ivy Bridge. If Intel had used scan/ATPG then this attack could not have worked even in theory. Unfortunately, I don't have the insight to understand why scan/ATPG could introduce a backdoor.

Disclaimer: I don't think that this attack is even theoretically feasible given just a few real world constraints. I am just nitpicking

Scan chains by design, give you the ability to load each flop with whatever value you want. Then you can toggle the clock and see the result. If you were very resilient about this you may be able to gather information about the structure. Without a GDS or netlist this is all very far fetched and unlikely. I've said before, but it is far more likely to bribe a rogue designer than to introduce back doors at this level.