CUDA Performance: Maximizing Instruction-Level Parallelism

Re:CUDA Performance: Maximizing Instruction-Level Parallelism by lmeyerov on Friday September 06, 2013 @11:43PM (#6343871)

A labmate did some great work similar to Continuum's wrapper and has been continuing on now at NVIDIA: http://copperhead.github.io/ . He basically identified an ML-like subset of Python (sort of like asm.js vs js) and specializes it.

For me, the big surprise is that Copperhead departs from NESL-like flattening transformations (e.g., those used by Data Parallel Haskell.) It's a bit less surprising when you realize the creator is a GPU expert :)

Edit: Vasily, the guy behind the paper advertised in Continuum's blog post, is also from our lab ;-)

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Re:CUDA Performance: Maximizing Instruction-Level Parallelism by iskander on Monday September 09, 2013 @02:10PM (#6355115)

Is Bryan still working on Copperhead?

Also, do you know if the DPH folks ever managed to iron out a version of higher order flattening which gives a predictable performance gain?

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Re:CUDA Performance: Maximizing Instruction-Level Parallelism by lmeyerov on Monday September 16, 2013 @04:42PM (#6395765)

I think Bryan has been doing a followup to Copperhead, probably easy to just ask him :)

I don't know what you mean by predictable performance. Flattening is a direct transformation and seems simple to reason about on SIMD architectures, though the recent dynamic schedule (work stealing) approach for multicore/distributed has the usual caveats. (I tend to avoid it for HPC.) Given the 10+ year history of the researchers involved, it seems like a slow-but-steady project..

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