There has been a lot of back-and-forth over this, I've done my own research and I think that it is possible to make some degree of ASIC in about a year.

Specifically this would be something called a 'structured' ASIC. If you get it right the first time (always a big question) then under a year is doable. A structured ASIC isn't nearly as efficient as a real special purpose design, it will consume more power and will fall speedwise somewhere between an FPGA and a true custom ASIC, probably closer to the FPGA end.

There are currently three companies that claim to be working on ASICs, only one of those three I think has the chops to pull it off.

But anybody that paid their money up-front to these companies without a shipping product is really slightly out of their mind.

All of the companies have insisted that they're not selling structured ASICs, though.

Designing an ASIC that only does SHA256 really fast should be a lot faster than an ASIC that does more than one thing, right?

Isn't the idea of ASIC's in general that they are only supposed to do one thing?

https://en.wikipedia.org/wiki/ASIC "As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 gates to over 100 million. Modern ASICs often include entire microprocessors, memory blocks including ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often termed a SoC (system-on-chip)."