Thanks for sharing, will take a proper look later, but looks like you model latency which is something I wanted to include but couldn't think of a way that wouldn't take away from the simplicity of the model.

I agree code as source of truth is a must and GUI is not necessary for authoring, everything I built (Snake, Pong, the RISCV CPU) was done headlessly in node with the help of Claude working to a spec just using the @simten/core lib on npm.

I just built a readonly ui-layer on top with the hope of making it more accessible to students/learners starting out in the space, the main features being able to visually scrub between cycles and drill down into the internals of an abstracted component. I also have a Verilog import thing I've been working on to allow learners to visualise and poke around in the browser