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A comment on RISC-V: They should have known better. Parent comment

Re:RISC-V: They should have known better by zephen on Friday August 14, 2026 @08:30PM (#49306296)
> RISC-V is... fine

Exactly.

> It satisfies my two requirements for an ISA as a hobby CPU designer...

You probably have some unstated requirements as well, such as available toolchains and "vetted well enough to actually be able to run code."

Risc-V now occupies the Schelling point for people who, for whatever reason (rent-seeking and security top the list) want to leave the x86 and Arm ecosystems.

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Re:RISC-V: They should have known better by andrewflnr on Friday August 14, 2026 @08:39PM (#49306358)
They did explicitly specify:

> 1. Supported in mainline LLVM and GCC.

Which pretty well encapsulates the ecosystem requirements.

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Re:RISC-V: They should have known better by brucehoult on Saturday August 15, 2026 @12:38AM (#49307687)
Luke is too modest. Something in the region of 5 million chips containing his hobby CPU have shipped since launch on August 8, 2024.
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Re:RISC-V: They should have known better by dgellow on Saturday August 15, 2026 @01:53PM (#49312679)
Could you share a link or more details? What is this hobby CPU project?
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Re:RISC-V: They should have known better by aurelian15 on Saturday August 15, 2026 @02:29PM (#49313013)
I think the GP is talking about the Hazard3 [1] core. This is one of the CPU cores besides the ARM M33 instantiated on the RP2350 µC [2]. See this article from Luke Wren (Wren6991) back when the RP2350 came out [3].

[1] https://github.com/Wren6991/Hazard3

[2] https://www.raspberrypi.com/products/rp2350/

[3] https://www.raspberrypi.com/news/risc-v-on-raspberry-pi-pico...

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Re:RISC-V: They should have known better by dgellow on Saturday August 15, 2026 @02:38PM (#49313114)
Thank you!
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Re:RISC-V: They should have known better by ACCount37 on Saturday August 15, 2026 @06:42PM (#49314969)
What I find interesting is that RP2350 is designed as "one or the other", no way to use ARM and RISC-V concurrently, and has fuses that can kill ARM M33 cores outright.

Makes me wonder if an "ARM cores fused off, RISC-V only, no ARM fees" SKU is possible.

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Re:RISC-V: They should have known better by LukeShu on Saturday August 15, 2026 @10:39PM (#49316413)
Several of the peripherals in the RP2350 are also ARM IP.
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Re:RISC-V: They should have known better by brucehoult on Sunday August 16, 2026 @01:21AM (#49317142)
You can choose Arm in one pair and RISC-V in the other pair if you want.
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Re:RISC-V: They should have known better by LukeShu on Saturday August 15, 2026 @02:21PM (#49312923)
Luke Wren works at Raspberry Pi and designed the Hazard3 CPU core that is in the RP2350 chip.
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Re:RISC-V: They should have known better by mrheosuper on Sunday August 16, 2026 @11:05PM (#49326136)
Are we talking about rp2350 ? Because the rp2350 can be config as pure arm soc.

In fact, if we are talking about successfull riscv soc, RISC-V esp32 may have better chance

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