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A comment on Samsung Demonstrates 3D Stacked FETs with Triple Nanosheet Channels at 42nm. Parent comment
Reducing trace length seems to be the way forward for faster/larger circuits. Signal propagation time on-die is becoming an issue.
Things like Huawei's Logic folding, or TSVs, and so on, attack the issue by reducing signal travel time.
This looks like another building block in that direction.
There's also some push at cooling chips from both sides.
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Reducing trace length seems to be the way forward for faster/larger circuits. Signal propagation time on-die is becoming an issue.
Things like Huawei's Logic folding, or TSVs, and so on, attack the issue by reducing signal travel time.
This looks like another building block in that direction.
There's also some push at cooling chips from both sides.