Re:XOR'ing a register with itself is the idiom for zeroing i...
by tom_ on Wednesday April 22, 2026 @09:47PM
(#47871457)
Are you sure you're not an LLM? There is no way anybody writing 6502 would do anything else, because there's no other way to do it.
(You can squeeze in a cheeky Txx instruction afterwards to get a 2-or-more-for-1, if that would be what you need - but this only saves bytes. Every instruction on the 6502 takes 2+ cycles! You could have done repeated immediate loads. The cycle count would be the same and the code would be more general.)
Re:XOR'ing a register with itself is the idiom for zeroing i...
by repelsteeltje on Thursday April 23, 2026 @09:19AM
(#47875445)
> Are you sure you're not an LLM?
Hard to tell, but I don't think so ;-)
I suppose using Txx instructions rather than LDx is more of an idiom than intended to conserve space. Also, could an LDx #0 potentially be 3 cycles in the edge case where the PC crosses a page boundary? (I'm probably confused? Red herring?)
Re:XOR'ing a register with itself is the idiom for zeroing i...
by tom_ on Thursday April 23, 2026 @08:45PM
(#47884156)
I don't know how the 6502's PC increment actually worked, but it was an exception to the general rule of page crossings (or the possibility thereof) incurring a penalty, or, as was also sometimes the case, just ignored entirely. (One big advantage of the latter approach: doing nothing does take 0 cycles.)
The full 16 bits would be incremented after each instruction byte fetched, and it didn't cost any extra if there was a carry out of the MSB.
The 6502 gets by doing immediate load: 2 clock cycles, 2 bytes (frequently followed by single byte register transfer instruction). Out of curiosity I did a quick scan of the MOS 1.20 rom of the BBC micro: