RAM Has a Design Flaw from 1966. I Bypassed It [video]

Re:RAM Has a Design Flaw from 1966. I Bypassed It [video] by strongpigeon on Friday April 10, 2026 @10:54AM (#47719085)

> At a high level it’s a bit contradictory; trying to reduce the tail latency of cold reads by doubling the cache footprint makes every other read even colder.

That’s my main hang up as well. On one hand this is undeniably cool work, but on the other, efficient cache usage is how you maximize throughput.

This optimizes for (narrow) tail latency, but I do wonder at what performance cost. I would be super interested in hearing about real world use cases.

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Re:RAM Has a Design Flaw from 1966. I Bypassed It [video] by deegu on Friday April 10, 2026 @11:48AM (#47719917)

This might be useful in a case where a small lookup or similar is often pushed out from cache such that lookups are usually cold. Yet lookup data might by small enough to not cause issue with cache pollution, increased bandwidth or memory consumption.

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Re:RAM Has a Design Flaw from 1966. I Bypassed It [video] by foltik on Friday April 10, 2026 @02:03PM (#47721633)

In this case it’s better to asynchronously bring the data into the cache, which you can do with a prefetch shortly before the read.

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Re:RAM Has a Design Flaw from 1966. I Bypassed It [video] by deegu on Friday April 10, 2026 @05:18PM (#47723773)

Perhaps. Then again, if your target is to reduce dram refresh induced latency, you might not have time to prefetch either.

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