Re:RAM Has a Design Flaw from 1966. I Bypassed It [video]
by foltik on Friday April 10, 2026 @10:00AM
(#47718293)
Yeah exactly, and it’s absolutely dwarfed by the tail latency of going to DRAM in the first place. A cache miss is a 100x tail event vs. an L1 hit. The refresh stall is a further 5x on top of that, which barely registers if you’re already eating the DRAM cost.
Re:RAM Has a Design Flaw from 1966. I Bypassed It [video]
by ufocia on Saturday April 11, 2026 @10:32AM
(#47730976)
It could be useful for large data set lookups where you're still limited to largely commodity hardware.
Not sure how ~2-8x hardware costs needed to implement this reasonably would compare with costs of specialized hardware.
Isn't that rather trivial though as a source of tail latency? There's much worse spikes coming from other sources, e.g. power management states within the CPU and possibly other hardware. At the end of the day, this is why simple microcontrollers are still preferred for hard RT workloads. This work doesn't change that in any way.