Re:Developing a BLAS Library for the AMD AI Engine [pdf]
by titanix88 on Saturday January 03, 2026 @11:02PM
(#46484757)
Looks like the author have not used software pipelining compiler directives with the kernel loops. AMD AIE architecture has 5 cycle load/store latency and 7 cycle FP unit latency. With software pipelining, they could have 5-10x speed up for long loops.
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