Re:Multi-core and multi-threading performance
by jbooth on Thursday October 11, 2012 @10:47AM
(#4640982)
I agree with everything you're saying, I just think the 'obvious point' is one that's papered over in the public discourse a lot because it's not exciting.
It is interesting why they don't scale linearly and I agree that it's probably a combination of memory bus contention and/or the chip itself being a little slower.
The whole bulldozer thing seemed like a marketing stunt rather than thoughtful pursuit of higher performance to me. Given the frequency and cost of cache miss rates, Intel HT seems to get the same work done on fewer watts.
Re:Multi-core and multi-threading performance
by marshray on Thursday October 11, 2012 @11:12AM
(#4641102)
I really don't think AMD would have bet their next generation of chips on something they believed was a marketing stunt.
Once the upcoming chip changes get explained to the Marketing Department, however, maybe it kinda starts to sound like Marketing.
Re:Multi-core and multi-threading performance
by frozenport on Thursday October 11, 2012 @11:53AM
(#4641340)
Intel HT is often disabled on HPC clusters due to performance problems. Also many people refer to the IL as a 8 core CPU due to the problems mentioned above. Much like not using the HT, many codes disable half the AMD chip.
Re:Multi-core and multi-threading performance
by jbooth on Thursday October 11, 2012 @12:04PM
(#4641396)
Yeah, but it's really only on highly-optimized cache-coherent vector/matrix math that it's a problem. On just about every other piece of software, it works great.
I feel like AMD saw the benchmarks available for matrix math and went for it, rather than thinking about what real-world performance profiles looked like.
I'm not trying to pick on the article, I like it overall. I took an interest in the Anand article when I learned you could build a 64-core box for about $4000.
This is the article it's in response to http://www.anandtech.com/show/5057/the-bulldozer-aftermath-d... the crux of which is:
Some, including sources inside AMD, have blamed Global Foundries for not delivering higher clocked SKUs. Sure, the clock speed targets for Interlagos were probably closer to 3GHz instead of 2.3GHz. But that does not explain why the extra integer cores do not deliver. We were promised up to 50% higher performance thanks to the 33% extra cores, but we got 20% at the most.
So the real questions seem to be:
Is Interlagos' perfomance disappointing on pure-parallel benchmarks as well, or just those with a noticeable serial bottleneck?
If there is poor scalability, what is the cause?
and perhaps most importantly: Will my kind of workload actually benefit from Interlagos' more cores?
I think that probably what's happening is that even the pure parallel benchmarks are not scaling linearly relative to the previous generation of chips, the reason is a combination of architectural changes in the core itself and memory bus contention, and the target market for these chips is VPS hosts running hundreds of VM images.