This little chip could be a significant boon to signal and image processing. A number of those applications, particularly surveillance radar, sesimic/hydrographic survey, and sensor fusion[1], have signficant data parallelism. Many have multiple independent data streams that must be processed and integrated in real time. With the proper algorithms, an architecture like this is much more efficient than a general-purpose multi-core or multi-machine system.

One of the key limits to these sensors is the data pipe between the various pieces that run the signal processing. This is especially true when one of the hops is over a relatively slow link, such as with an ROV/UAV. The size and weight of this chip would allow more of the signal processing to be embedded on the platform or in the sensor, thus reducing the volume of data passed over the slow link and allowing more information to be sent.

It does, of course, require a different programming paradigm to use effectively. Special applications like I have mentioned are worth the extra effort and reduced portability and so will see value in this device. No doubt some other applications mentioned so far (crypto, finance, etc) will also see value in it as well.

[1] I have a strong background in and knowledge of military sensors, and signficant exposure to seismic and hydrographic survey in the oil and gas industry.