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Re:Writing a RISC-V Emulator in Rust by 6SixTy on Sunday October 26, 2025 @12:45PM (#45713241)
The rundown on this is that CodeThink added Big Endian RISC-V because of a half-baked optimized networking scenario where somehow the harts (RISC-V speak for a cpu core) don't have Zbb byte manipulation instructions. Linus shuts down efforts made in mainline Kernel (!!) because these issues are extremely flimsy at best and don't have technical merit for complicating the kernel's RISC-V code and already extreme RISC-V fragmentation.

I've looked at more reasons that CodeThink came up with for Big Endian RISC-V, and trust me, that's the best that they have to present.

Re:Writing a RISC-V Emulator in Rust by crote on Sunday October 26, 2025 @03:23PM (#45714500)
> somehow the harts don't have Zbb byte manipulation instructions

More specifically, it relies on a hypothetical scenario where building a big-endian / bi-endian core from scratch would be easier than adding the Zbb extension to a little-endian core.