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A comment on Designing a Low Latency 10G Ethernet Core (2023). Parent comment

Re:Designing a Low Latency 10G Ethernet Core (2023) by mrlongroots on Thursday October 09, 2025 @02:41AM (#45524304)
The other funny bit is that one-way PCIe latency is 250ns-ish (don't quote me on the exact numbers), which imposes a hard 1us constraint on latency between two hosts.
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Re:Designing a Low Latency 10G Ethernet Core (2023) by mgrosvenor on Thursday October 09, 2025 @07:34AM (#45526230)
You can go quicker with CXL, but not by much.
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Re:Designing a Low Latency 10G Ethernet Core (2023) by foobar10000 on Thursday October 09, 2025 @08:02AM (#45526456)
There are always DPUs like NextSilicon, Bleu*, etc - at under 100 ns of SoF to fast compute though.
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