AMD Claims Arm ISA Doesn't Offer Efficiency Advantage over x86

Re:AMD Claims Arm ISA Doesn't Offer Efficiency Advantage ove... by jabl on Tuesday September 09, 2025 @07:03AM (#45180364)

> x86 also has flags, which add implicit dependencies between instructions, and must make designer's life harder.

Fortunately flags (or even individual flag bits) can be renamed just like other registers, removing that bottleneck. And some architectures that use flag registers, like aarch64, have additional arithmetic instructions which don't update the flag register.

Using flag registers brings benefits as well. E.g. conditional jump distances can be much larger (e.g. 1 MB in aarch64 vs. 4K in RISC-V).

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Re:AMD Claims Arm ISA Doesn't Offer Efficiency Advantage ove... by adgjlsfhk1 on Tuesday September 09, 2025 @03:58PM (#45187899)

How big a difference is that? 1MB is still too small to jump to an arbitrary function, and 4K is big enough to almost always jump within a function.

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