Re:AMD Claims Arm ISA Doesn't Offer Efficiency Advantage ove...
by fulafel on Tuesday September 09, 2025 @01:29AM
(#45177753)
No, it's about the same bottleneck that also explains the tapering off of single core performance. We can't extract more parallelism from the single flow-of-control of programs, because operations (and esp control flow transfers) are dependent on results of previous operations.
SMT is about addressing the underutilization of execution resources where your 6-wide superscalar processor gets 2.0 ILP.
SMT is about addressing the underutilization of execution resources where your 6-wide superscalar processor gets 2.0 ILP.
See eg https://my.eng.utah.edu/~cs6810/pres/6810-09.pdf