Re:AMD Claims Arm ISA Doesn't Offer Efficiency Advantage ove...
by eigenform on Tuesday September 09, 2025 @12:06AM
(#45177266)
Don't know this for certain, but I always assumed that x86 implementations get away with this by predecoding cachelines. If you're going to do prefetching in parallel and decoupled from everything else, might as well move part of the work there too? (Plus, you can identify branches early!)
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