AMD Claims Arm ISA Doesn't Offer Efficiency Advantage over x86

Re:AMD Claims Arm ISA Doesn't Offer Efficiency Advantage ove... by adgjlsfhk1 on Monday September 08, 2025 @05:58PM (#45174572)

pure decoder width isn't enough to tell you everything. X86 has some commonly used ridiculously compact instructions (e.g. lea) that would turn into 2-3 instructions on most other architectures.

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Re:AMD Claims Arm ISA Doesn't Offer Efficiency Advantage ove... by kimixa on Monday September 08, 2025 @06:07PM (#45174660)

Also the op cache - if it hits that the decoder is completely skipped.

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Re:AMD Claims Arm ISA Doesn't Offer Efficiency Advantage ove... by ajross on Monday September 08, 2025 @07:03PM (#45175269)

The whole ModRM addressing encoding (to which LEA is basically a front end) is actually really compact, and compilers have gotten frightently good at exploiting it. Just look at the disassembly for some non-trivial code sometime and see what it's doing.

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Re:AMD Claims Arm ISA Doesn't Offer Efficiency Advantage ove... by monocasa on Monday September 08, 2025 @11:01PM (#45176895)

Additionally, stuff llike rmw instructions are really like at least three, maybe four or five risc instructions.

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Re:AMD Claims Arm ISA Doesn't Offer Efficiency Advantage ove... by ack_complete on Tuesday September 09, 2025 @10:39AM (#45182568)

Yes, but so does ARM. ld1 {v0.16b,v1.16b,v2.16b,v3.16b},x0,#64 loads 4 x 128-bit vector registers and post-increments a pointer register.

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