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A comment on AMD Claims Arm ISA Doesn't Offer Efficiency Advantage over x86. Parent comment

Re:AMD Claims Arm ISA Doesn't Offer Efficiency Advantage ove... by adgjlsfhk1 on Monday September 08, 2025 @05:29PM (#45174266)
sure, but Arm has Neon/sve which impose basically the same requirements for vector instructions, and most high performance arm implimentations have a wide suite of crypto instructions (e.g. Apple's M series chips have AES, SHA1 and Sha256 instructions)
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Re:AMD Claims Arm ISA Doesn't Offer Efficiency Advantage ove... by camel-cdr on Tuesday September 09, 2025 @02:18AM (#45178083)
Neon has it worse, because it's harder to scale issue width then vector length.

Zen5 has four issue 512-bit ALUs, current Arm processors have been stuck at four issue 128-bit for years.

Issue width scales quadratically, while vector length mostly scales linearly.

Intel decided it is easier to rewrite all performance critical applications thrice then to go wider than four issue SIMD.

It will have to be seen if Arm is in a position to push software ro adopt SVE, but currently it looks very bleak, with much of the little SVE code thats out there just assuming 128-bit SVE, because thats what all of the hardware is.

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