Disks lie. And the controllers that run them are partners in crime.

Re:Disks lie. And the controllers that run them are partners... by ChuckMcM on Saturday September 08, 2012 @11:30AM (#4493112)

True, if you look at Intel's flash chips they do this internally, you've got the flash 'controller' which sits astride a bunch of actual flash being written in parallel and its doing the wear leveling. I've played a bit with Intel's PCIe attached flash and can vouch for it being quite a bit faster than going through the SATA port, now if we can get them to move it to the FSB so that I can talk to it via the L1/L2/L3 cache then I'll be really happy.

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Re:Disks lie. And the controllers that run them are partners... by baruch on Saturday September 08, 2012 @03:09PM (#4493684)

That's an interesting concept but there would still be a need for the much faster and non-volatile DRAM. At which point you need to discern which is which and decide for each data structure where you want to locate it.

The latency of NAND flash will be so much more than DRAM that you'd have to use DRAM as the cache layer before the flash in which case you could just use one of those block caching schemes coupled with a PCIe SSD to get everything that is good with very little trouble at the architecture level.

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Re:Disks lie. And the controllers that run them are partners... by ChuckMcM on Saturday September 08, 2012 @05:29PM (#4494060)

Absolutely, there will always be a place for DRAM (in bulk 'fast' memory) and for Static RAM (in caches), this is just a new (for this generation) tier beyond DRAM.

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