News for hackers. Stuff that matters.

A comment on The Sail instruction-set semantics specification language.

Re:The Sail instruction-set semantics specification language by Cieric on Saturday July 26, 2025 @07:22PM (#44697703)
I really like the idea of this. I wonder if I can convince my work to use it for our hardware. Are things like SIMD, SIMT, and other weird formats easy to represent in this kind of language? Or should I just assume anything describable in Verilog/HDL can be described in this language.

This also brings up another question if anyone knows. Is there a term for hardware description languages similar to turning complete for programming languages, or is there a different set of common terms?

[ Parent | on HN ]
Re:The Sail instruction-set semantics specification language by timhh on Sunday July 27, 2025 @03:59AM (#44699628)
Yeah you can describe basically any ISA including SIMD. The RISC-V model doesn't support packed SIMD (the P extension) but it does support Vector.
[ Parent | on HN ]
Re:The Sail instruction-set semantics specification language by stolencode on Wednesday July 30, 2025 @05:11AM (#44732239)
This looks and feels like "Verilog Lite."
[ Parent | on HN ]