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Re:Released the schematics and PCB of my transputer ISA board by webdevver on Sunday July 06, 2025 @07:06AM (#44479644)
we need to bring back the cpu address/data bus pinout on the back of PCs

i want all 64 bits with a write strobe and a 3ghz clock. let me blink leds by bitbanging /dev/mem

Re:Released the schematics and PCB of my transputer ISA board by kragen on Sunday July 06, 2025 @11:57AM (#44481826)
That is less useful than you might expect due to issues of timing skew and signal reflections from transmission-line impedance mismatches.

SCSI was already contending with the termination problem in the early 90s; low-voltage differential SCSI was in the SCSI-3 standard from 01995, 30 years ago, in order to hit 80 megabytes per second over the kind of multidrop (bus) parallel interface you're talking about. That's twenty thousand times slower than the main system memory interface on the latest amd64 servers.

At the point where you already had to go to low-voltage differential signaling to get reliable communication, your bus is no longer a useful GPIO interface for blinking LEDs.

But if you have a 50¢ 16-line GPIO expander chip like https://www.digikey.com/en/products/detail/kinetic-technolog... somewhere on the SMBus the board is already using for things like temperature monitoring, maybe for some other minor interface function, all that's required is to run its GPIOs to test points and document them. Not as fast as the ISA bus but plenty of power for simple digital interfacing.

Re:Released the schematics and PCB of my transputer ISA board by dboreham on Sunday July 06, 2025 @01:07PM (#44482360)
Ironic that this comment is on an article about the Transputer where the entire point was to not use memory mapped I/O, instead only p2p message channels like today's PCIe.
Re:Released the schematics and PCB of my transputer ISA board by yjftsjthsd-h on Sunday July 06, 2025 @02:24PM (#44482916)
I think Raspberry Pis basically give you that via GPIO?