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Re:Designing a low-cost high-performance 10 MHz – 15 GHz vec... by henrikf on Tuesday April 15, 2025 @05:10PM (#43698431)
There's not much software. PC calculates PLL register values for correct LO and source output frequencies, and transfers them to the FPGA which writes them to the hardware. FPGA accumulates the downconverted samples from the receiver ADCs. Samples are transferred to PC which calculates ratios of the receiver outputs to get uncorrected S-parameters. scikit-rf Python library is used for calibration and plotting.
Re:Designing a low-cost high-performance 10 MHz – 15 GHz vec... by Neywiny on Tuesday April 15, 2025 @08:50PM (#43700158)
Any possibility of seeing the code (on github)? Seems interesting.