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A comment on Imec demonstrates electrical yield for 20nm lines High NA EUV single patterning. Parent comment

Re:Imec demonstrates electrical yield for 20nm lines High NA... by bri3d on Sunday March 02, 2025 @06:02PM (#43236203)
No, the gate length on most 5nm nodes is like 40nm or something. Since around 2008-ish, the “process name” and the size of any feature have rapidly diverged (even if you use some weird pointless metric like the size of a FinFET fin, nothing on 5nm measures 5nm).

Ironically, prior to 2008 the process name was backwards the other way, for example 130nm process usually has something like 70nm gates.

It’s always really just been a marketing thing anyway, since the possible density of a given logic unit in a given manufacturers process will differ due to a huge number of factors.

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Re:Imec demonstrates electrical yield for 20nm lines High NA... by thechao on Monday March 03, 2025 @09:58AM (#43242332)
Just to reiterate: in old-skool HS electricity terms, a transistor is going to need enough electrons. That number is pretty large, and is tied pretty strongly to materials and geometry. Those two things (materials & geometry) change far slower than Moore's law. What changes quickly is gate density and design cleverness.
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