> First, you claimed that there was no L3 BW test.

I claimed that they did not provide figures for L3 cache bandwidth. They did not.

> Now, I am not even sure if you're trolling me or lacking knowledge or what at this point?

You really should be grateful that a professional is taking time out of his day to explain things that you clearly do not understand.

> Please do tell what you consider a "proper test of L3 cache"? And why do you consider their test invalid?

You cannot measure L3 cache performance by measuring the bandwidth on a region of memory larger than the L3 cache. What they did is a partially cached test and it does not necessarily reflect the true L3 cache performance.

> I am curious because triggering 32 physical core threads to run over 32 independent chunks of data (totaling 3G and not 128M) seems like a pretty valid read BW experiment to me.

This does not test L3 cache bandwidth at all. This would be a generic memory bandwidth test. Their graphs showing performance at different amounts of memory is designed to show the performance of the memory hierarchy. The moment you exceed the amount of cache at a certain level, the performance transitions to different level. They did benchmarks on different amounts of memory to get the points in their graph and connected them.

> Right, but you missed the part that former is configured for the server market and the latter for the client market. Two different things, two different chips, different memory controllers if you wish. That's why you cannot compare one to each other directly without caveats.

The Xeon Max chips with its HBM2e memory is the one place where 2 AVX-512 loads per cycle could be expected to be useful, but due to internal bottlenecks they are not.

Also, for what it is worth, Intel treats AVX-512 as a server only feature these days, so if you are talking about Intel CPUs and AVX-512, you are talking about servers.

> But that's what you said trying to refute the fact why Intel was in a lead over AMD up until zen5? You're claiming that AVX-512 workloads and load-store BW are largely irrelevant because CPUs are anyway bottlenecked by the system memory bandwidth.

I never claimed AVX-512 workloads were irrelevant. I claimed doing more than 1 load per cycle on AVX-512 was irrelevant because you are going to be bottlenecked on the first load operation for anything that is memory bandwidth bound. Intel losing its lead to AMD is due to entirely different reasons than AVX-512 loads per cycle. This is obvious when you consider that most workloads do not touch AVX-512.

To be clear, when you can use AVX-512, it is useful, but the ability to do 2 loads per cycle does not add to the usefulness very much.

> I am all ears to hear what datacenter workloads you have in mind that are CPU-bound?

Note that I said compute bound, not CPU bound. Nearly all datacenter workloads run on CPUs are compute bound. Memory bandwidth bound things are better run on GPUs, which have far more memory bandwidth.

> Any workload besides the most simplest one is at some point bound by the memory BW.

This is wrong. It does not matter how many experts you consult. Every single one will try to explain the von Neumann bottleneck to you upon hearing this.

> You're contradicting your own claims by saying that cache is there to hide (cut) the latency but then you continue to say that this is irrelevant. Not sure what else to say here.

There is no contradiction. The cache is there to hide latency. It is largely not there to provide bandwidth. It only does as a side effect of being lower latency than system memory. The TACC explanation of how queuing theory applies to CPUs makes it very obvious that memory bandwidth is inversely proportional to memory access times, which is why the cache has more memory bandwidth than system RAM. It is a side effect of the actual purpose, which is to reduce memory latency.

> 99% of the datacenter machines are not attached to the GPU. Does that mean that 99% of datacenter workloads are not "truly exceptional" for whatever the definition of that formulation and they are therefore mostly CPU bound?

99% is a made up number. Your question is nonsensical.

You're going a long way not to address reasonably simple questions I had. You're very combative for no obvious reason - I think I had my arguments laid out in the most objective form I could but unfortunately you seem to be very triggered by those especially by the logical concerns I raised. You are in the wrong here simply because you're assuming that all the experience you have is representative of all other experience people have in this industry. There are much larger challenges than designing a filesystem, you know. No need to be so vain.

Not only you're ending up being very disrespectful but you're also pulling out the appeal to authority argument. Also something Brendan Gregg did on me here at HN meaning that no experience can substitute the amount of ego in some guys.

FWIW you can be let assured that you can't match my experience but that's not the argument I would ever pull off. I like to be proved wrong. This is a way I learn new things. BTW I designed my first CPU 15 years ago but during the career I learned to put my ego aside, discuss objectively, think critically and learn on my own reasoning mistakes from other people. Many of these points you are obviously lacking so this is a waste of time for me - I see no way to drive this discussion further but thanks anyway.