Re:Kronos: Soviet Processor Family for High-Level Languages ...
by mbitsnbites on Sunday October 27, 2024 @08:36AM
(#41962148)
I'd argue that x86 and IBM z/Arch are the ones that stick out among contemporary ISAs in that they need fairly complex fron-end translation into an internal instruction format.
ARM implementations that support both ARMv7 (both ARM mode and THUMB mode) and ARMv8 also need some kind of translation in the front-end, but recent ARMs (like Apple's implementations) don't support 32-bit mode and are simpler in that way.
Most other ISAs are much closer to the metal, although many implementations still do some level of translation in the front-end (mostly fusing/splitting certain instruction combinations for better efficiency). Examples: ARMv8+, RISC-V, MIPS, Loongson, TI 6x & 7x DSP, and of course most GPUs (and my own MRISC32 ISA).
ARM, mostly. Instructions are 32 bits wide and aligned on 4-byte boundaries. This simplifies instruction decode. IA-32 does not require this, leading to considerable complexity in superscalar instruction fetch and decode.
The ARM instruction set isn't very "reduced" any more.[1] Despite this, on larger CPUs, most instructions in modern CPUs have direct hardware implementations. There are enough transistors available to do it that way.
[1] file:///home/john/Downloads/arm_instruction_set_reference_guide_100076_0100_00_en.pdf