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A comment on AMD's Turin: 5th Gen EPYC Launched. Parent comment

Re:AMD's Turin: 5th Gen EPYC Launched by nullc on Sunday October 13, 2024 @01:29PM (#41829805)
9684x is 1152 MB cache per socket, 12 CCDs * 96MB. A similar X series zen5 is planned.

Though I wish they did some chips with 128GB of high bandwidth dram instead of a extra sized sram caches.

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