Re:AMD's Turin: 5th Gen EPYC Launched
by bee_rider on Saturday October 12, 2024 @11:50AM
(#41819986)
I would be pretty curious about such a system. Or, maybe more practically, it might be interesting to have a system pretends the L3 cache is ram, and the ram is the hard drive (in particular, ram could disguise itself as the swap partition, to so the OS would treat is as basically a chunk of ram that it would rather not use).
[ Parent
| on HN ]
Re:AMD's Turin: 5th Gen EPYC Launched
by compressedgas on Saturday October 12, 2024 @12:01PM
(#41820077)
Philip Machanick's RAMpage! (ca. 2000)
> The RAMpage memory hierarchy is an alternative to a conventional cache-based hierarchy, in which the lowest-level cache is managed as a paged memory, and DRAM becomes a paging device.
So, essentially, you're just doing cache eviction in software. That's obviously a lot of overhead, but at least it gives you eviction control. However, there is very little to do when it comes to cache eviction. The algorithms are all well known and there is little innovation in that space. So baking that into the hardware is always better, for now.