That's funny, I had thought that memristors were a solved problem based on this talk from a while back (2010!): https://www.youtube.com/watch?v=bKGhvKyjgLY, but I gather HP never really commercialized the technology. More recently, there does seem to be interest in and research on the topic for the reasons you and the GP post noted (e.g., https://www.nature.com/articles/s41586-023-05759-5).

I believe asianometry did a YouTube video on memristors....might be worth watching.

Or even an architecture akin to an atonishingly large number of RP2050's. It does seem like it would work well for certain types of nnet architectures.

I've always been partial to the idea of two parallel surfaces with optical links, Make a connection machine style hypercube where the bit of the ID of every processor indicates its location in the hypercube. Place all of the even parity CPUs on one surface and the odd parity CPUs on the other surface, every CPU would have line of sight on its neighbour in the hypercube (as well as the diametrically opposed CPU with all the ID bits flipped)

> Or even an architecture akin to an atonishingly large number of RP2050's.

Groq and Cerebras are probably that kind of architecture

It came and went in the form of optane.

I'm a layman on this topic, so I'm definitely about to say something wrong. But I recall an intriguing idea about a sort of "reversion to analog," whereby we use the full range of voltage crossing a resistor. Instead of cutting it in half to produce binary (high voltage is 1, low voltage is 0), we could treat the voltage as a scalar weight within a network of resistors.

Has anyone else heard of this idea or have any insight on it?

The question then emerges: how do we program these things?

Sara Acour has some answers, e.g. https://scholar.google.com/citations?view_op=view_citation&h...