Re:The Pentium as a Navajo Weaving
by Taniwha on Sunday September 01, 2024 @08:36PM
(#41421529)
I'm building a stained glass window for our front entrance, as a sometimes chip designer it's going to be a half adder (so much much smaller than a pentium) - the big challenge is showing all the layers (si, implantation, poly, metal, vias etc) I'm only doing 1 level of metal. The result is going to be more of a thin layered sculpture than a traditional stained glass window
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Don't bother with the rectilinear pakeha layouts, do your half adders in curvilinear patterns, Koru style
I am pakeha and tangata triti .... now I have an idea for the next window (I was thinking about a neuron ...)
AHh gotcha.
Well yeah I reckon you render a full custom 4004 w/ koru patterned transistors into about 4m x 4m stained glass panel. Would look good as the foyer panel for the CS dept at the University of Waikato
Probably best to tape it out to https://tinytapeout.com/ first
Do they support curvilinear cells?
The simple openlane flow just uses standard cells, but you have the ability to just tape out polygons so curvyish is possible
(I already have a 4-bit CPU there)
Re:The Pentium as a Navajo Weaving
by bankcust08385 on Sunday September 01, 2024 @09:05PM
(#41421657)
Neat. 2 RTL gates -> 16 CMOS transistors (10 for XOR and 6 for OR)
Actually I misspoke, it's a full adder and very similar to the one on page 5 here
this sounds awesome! do you have drawings?
Yes, I'm at the cut cartoon stage, just choosing glass it's a long thin panel so I needed a design of about the same shape - what I'm building (actually a full adder, I misspoke above) looks a lot like the design on page 5 here