The largest out-of-order CPUs are actually quite reliant on having high-performance decode that can be performed in parallel using multiple hardware units. Starting from a simplified instruction set with less legacy baggage can be an advantage in this context. RISC-V is also pretty unique among 64-bit RISC ISA's wrt. including compressed instructions support, which gives it code density comparable to x86 at a vastly improved simplicity of decode (For example, it only needs to read a few bits to determine which insns are 16-bit vs. 32-bit length).

Except this isn't actually true.

> Does getting rid of dramatically increase the performance ceiling? Probably not.

No but it dramatically DECREASES the amount of investment necessary to reach that ceiling.

Assume you have 2 teams, each get the same amount of money. Then ask them to make the highest performing spec compatible chip. What team is gone win 99% of the time?

> And the flexibility of being able to implement a complex operation in microcode, or silicon is essential for CPU designers.

You can add microcode to a RISC-V chip if you want, most people just don't want to.

> The real benefit of RISC-V is anybody can use it.

That is true, but its also just a much better instruction set then x86 -_-

False premise, as size tool shows RVA20(RV64GC) binaries were already smallest among 64bit architectures.

Code gets smaller still (rather than larger) with newer extensions such as B in RVA22.

As of recently, the same is true in 32bit when comparing rv32 against former best (thumb2). But it was quite close before to begin with.