News for hackers. Stuff that matters.

A comment on Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V. Parent comment

Re:Box64 and RISC-V in 2024: What It Takes to Run the Witche... by fanf2 on Tuesday August 27, 2024 @05:20AM (#41365732)
Not small instruction sets, simplified instruction sets. RISC’s main trick is to reduce the number of addressing modes (eg, no memory indirect instructions) and reduce the number of memory operands per instruction to 0 or 1. Use the instruction encoding space for more registers instead.

The surviving CISCs, x86 and z390 are the least CISCy CISCs. The surviving RISCs, arm and power, are the least RISCy RISCs.

RISC V is a weird throwback in some aspects of its instruction set design.

[ Parent | on HN ]
Re:Box64 and RISC-V in 2024: What It Takes to Run the Witche... by panick21_ on Tuesday August 27, 2024 @10:01AM (#41367633)
Lets be real, its about business models. POWER was and is backed by IBM. ARM won on mobile. Does this mean POWER and ARM are better then MIPS, SPARC, PA-RISC, Am29000, i860? I don't think so.
[ Parent | on HN ]
Re:Box64 and RISC-V in 2024: What It Takes to Run the Witche... by Symmetry on Wednesday August 28, 2024 @07:21AM (#41378302)
More details on how RISCy or CISCy various chips are:

https://userpages.umbc.edu/~vijay/mashey.on.risc.html

Notably x86 is one of the less CISCy CISCs so it looks like there might be a happy medium.

[ Parent | on HN ]