Re:Faulty instructions in C910 RISC-V CPUs
by Arnavion on Monday August 12, 2024 @01:44PM
(#41227233)
Is it the logical end that we have custom cores everywhere? Yes RISC-V is open and relatively straightforward to implement (coincidentally I did just that over the weekend in a circuit simulator game), but I can also see economies of scale making it so that a few vendors end up making cores that are good enough for all use cases between them and end up dominating the market. A few low-powered 32E cores, a few desktop-grade 64GCBV... alphabet soup (or more likely, hanzi lamian) cores, and a few in between would seem to be enough.
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Re:Faulty instructions in C910 RISC-V CPUs
by dwoxctbvgq on Monday August 12, 2024 @06:57PM
(#41230310)
May I ask what circuit simulator game? I've attempted something similar with my very limited and hobby level hardware knowledge in Virtual Circuit Board and I learned that it would take me much longer than a weekend, heh.
Re:Faulty instructions in C910 RISC-V CPUs
by Arnavion on Monday August 12, 2024 @07:13PM
(#41230435)
Turing Complete - https://store.steampowered.com/app/1444480/Turing_Complete/
I also made my own assembler as part of learning the ISA and put it at https://github.com/Arnavion/riscv . You can see a screenshot and video of the CPU in action there.
The game's campaign walks you through creating a simple 8-bit CPU and then a larger CPU similar to old ARM. But then it also has a sandbox to do whatever, and you can use whatever design you want to solve the puzzles intended for the original two CPUs.